Digital-to-Time Converter 7 (DTC) based Phase Locked Loops 1 (PLLs) are gaining quickly in importance for LO frequency generation architectures. In context of digital and mixed signal ΔΣ PLLs 1, a DTC 7 can be used for realization of “true fractional dividers” as disclosed in D. Tasca, M. Zanuso, G. Marzin, S. S. C. Levantino and A. L. Lacaita, “A 2.9-4.0-GHz Fractional-N Digital PLL With Bang-Bang Phase Detector and 560-Integrated Jitter at 4.5-mW Power”, in JSSC, 2011 for example. In this disclosure, a DTC 7 is used in the feedback loop 4, which feedback loop 4 also includes the voltage controlled oscillator 6 (VCO) in an analog PLL or the digitally controlled oscillator 6 (DCO) in a digital PLL, after the divider 12, as depicted in FIG. 1 which shows a fractional-N DTC based PLL. The DTC 7 serves to compensate for instantaneous errors made by the integer divider 12 during fractional frequency synthesis. Using a DTC 7 in the described manner (a similar effect can be obtained by putting a DTC 7 on the reference path 2) permits a narrower input operation range of the Phase/Frequency Detector 11 (PFD) in analog or the Time-to-Digital Converter (TDC) 11 in digital PLLs 1. Relaxing the PFD 11 and TDC 11 design requirements (e.g. power, resolution and linearity) results in a significant power/performance boost since these blocks typically form the bottleneck for the overall synthesizer quality.
Moreover, a DTC 7 proved to be very useful for realization of the fractional-N sub-sampling PLL 1 or divider-less all-digital PLL 1 (ADPLL) architectures as disclosed in K. Raczkowski et al., “A 9.2-12.7 GHz wideband fractional-N subsampling PLL in 28 nm CMOS with 280 fs RMS jitter”, in JSSC, 2015 for example. In this disclosure, the DTC 7 is put on the reference path 2 as depicted in FIG. 2 which shows a fractional-N sub-sampling DTC based PLL. In FIG. 2, the DTC 7 produces controlled delays during the fractional synthesis to force sampling of the “VCO/DCO zero-crossings”, i.e. to compensate for the accumulated fractional residue difference between the input and the output phase. In this architecture, a (typically power consuming) divider 12 becomes redundant, which highlights the importance of the DTC 7 even more.
However, the DTC-based PLL 1 has the disadvantage that the DTC 7 introduces quantization, mismatch and nonlinearity errors which negatively influences the PLL output spectral purity by increasing phase noise and spurious content.
A possible solution for this problem is given in R. B. Staszewski et al., “Elimination of spurious noise due to time-to-digital converter”, in Circuits and Systems Workshop (DCAS), Dallas, 2009. In this disclosure, a DTC is put on the reference path and it is fed with a random code stream. The DTC serves as a dithering element and increases the input quantization noise which naturally helps in covering the PLL spurious content, especially close to integer PLL multiplication numbers.
Likewise, EP-A-2 339 753 discloses a PLL having a DTC on the reference path with the DTC having an adjustable time delay. In order to take account of the quantization error of the adjustable time delay a dithering element is used during calibration of the PLL.
However, these solutions have the disadvantage that they increase the quantization errors in the system and thus still have a negative influence on the PLL output spectral purity.